Modern radar signal processing plays a crucial role in enabling the full functionality of radar systems. This paper presents a comprehensive optimization of both the hardware architecture and software design of a radar signal processor, tailored to meet specific system requirements. The proposed system is built around four ADSP-TS201 chips and one FPGA, forming a high-performance signal processing board capable of performing space-time two-dimensional signal processing with just a single sub-board. Key algorithms such as adaptive sidelobe cancellation, 4-way pulse compression, MTI/MTD, sidelobe shadowing, and differential beam angle measurement are implemented to accurately determine target distance and azimuth deviation.
### 1. System Composition Analysis
The echo signal is combined with microwave signals on the antenna to generate sum and difference channel signals, along with two auxiliary antenna signals for IQ orthogonal interpolation. After downsampling by a factor of 1/8, four test channels are formed, each operating at a data rate of 128 MB/s. The system algorithm structure consists of three main modules: a sidelobe cancellation module, a digital pulse compression module, and an MTD processing module. Once the sum signal undergoes MTD (FFT-CFAR), the azimuth deviation is calculated using the sum and difference data if a target is detected.
Taking the low-frequency mode of radar operation as an example, the IQ data contains 5,388 points, with a re-frequency of 140 Hz. Considering a time margin, the system must process four signals within 6.7 ms. This demands that the system design must possess the following characteristics:
- High-performance floating-point processing capabilities to handle tasks like sidelobe cancellation, pulse compression, coherent accumulation, clutter mapping, and constant false alarm rate processing.
- Fast internal data transfer between processors and external memory expansion to manage large data volumes efficiently.
- External data and control interfaces, along with fault detection signal output.
- Extensive software optimization to ensure all processing modules are completed within a single pulse period.
### 2. Radar Processor Implementation
#### 2.1 Hardware Platform Design
Given the system's computational load and timing constraints, the signal processing board employs a multi-DSP parallel processing architecture. To achieve high-speed floating-point processing, a large data throughput, and sufficient memory capacity, the ADSP-TS201 chip from Analog Devices is selected. This high-performance DSP operates at up to 600 MHz, executing up to four instructions per cycle. It features dual independent arithmetic blocks, dual integer ALUs, and 24 MB/s of on-chip memory. Additionally, it includes 14 DMA controllers, four link ports, and four SDRAM controllers, allowing efficient data transfer and external memory expansion.
In multi-DSP designs, two common approaches are shared bus mode and link port coupling. While the shared bus offers a global address space, frequent inter-DSP communication can lead to bus contention and performance bottlenecks. In contrast, the link port coupling method provides independent memory spaces for each DSP, simplifying program debugging and reducing PCB complexity. Data transfer via the link port uses DMA, minimizing the impact on the DSP core’s computing time and improving real-time performance. Thus, four ADSP-TS201s are interconnected through link ports, forming a loosely coupled multi-DSP system capable of transferring up to 500 MB/s between any two DSPs.
The board is centered around four TS201 chips and one FPGA, supported by FLASH, SDRAM, and fiber optic components for data storage and transmission. The FPGA handles timing control, external data transmission, and bus communication with the DSPs. It connects to DSP0 and DSP1 via two independent 32-bit buses operating at 50 MHz, achieving a data transfer speed of 400 MB/s. The system clock runs at 50 MHz, with the TS201 operating at 600 MHz (12x). This configuration allows the board to achieve a peak processing capacity of 14.4 Gflops, meeting the system’s performance requirements.
#### 2.2 System Software Design and Optimization
Due to the complexity of the system algorithms and dynamic range requirements, the software is implemented on the DSP, allowing for flexible debugging and optimization. After microwave synthesis, the sum, difference, and two auxiliary channel signals are generated. Following A/D sampling of the orthogonal difference, the data is sent to the FPGA via fiber optics, where DSP0 receives and distributes the data to the other three DSPs. Each DSP processes one channel independently, as shown in the system flow diagram. After MTD processing, the results are returned to DSP1 for sidelobe and threshold detection, estimating the target’s azimuth deviation. The final result is transmitted back to the FPGA via DMA, completing the entire module within one pulse period, as illustrated in the software flowchart.
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